Routability Prediction of Network Topologies in FPGAs

A fundamental difference between ASICs and FPGAs is that the wires in ASICs are designed to match the requirements of a particular design. Conversely, in an FPGA, area is fixed and routing resources exist whether or not they are used. Modern FPGAs have the logic and routing resources to implement networks of multiprocessor systems, and system-level interconnection becomes a key element of the design process. In this paper we investigate how the resource usage affects the mapping of various network topologies to a modern FPGA routing structure. By exploring the routability of different multiprocessor network topologies between 8 and 64 nodes on a single FPGA, we illustrate that the resource utilization increases linearly for different topologies. Furthermore, the difference in logic resources and routing overhead for these topologies is not significant up to 60 nodes. We also show that ring topologies do not incur in congestion and they are limited in size by the available area of the die, whereas the size of fully-connected networks is limited by the available routing resources. Finally, we identify factors that impact the routability of multiprocessor systems on FPGAs and predict whether a particular multiprocessor system is routable and to approximate the operating frequency.